Chapter 3 – MOSFETs (switches)

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3.1 Concepts

A MOSFET is a semiconductor device with three terminals (or connections). Conduction between two terminals is controlled by the voltage level on the third control terminal.

Fig 3.1

This Figure is a black-box (vastly simplified) symbol for a MOSFET. Letters next to terminals stand for Gate, Drain, and Source (respectively). Gate is the control terminal.

To connect a MOSFET to our first circuit, we will have to satisfy the following criteria:

Voltage at the drain will be more positive than source.

Positive (>0V) control voltage will be applied to the Gate.

We will be using an N-channel enhancement mode device.

The circuit which satisfies criteria above looks like:

Fig 3.2

Where the battery with an arrow, on the left, is a variable voltage source, and A is an ammeter.

A practical circuit will use the same power supply to deliver variable voltage level to the gate, and will usually have a load instead of the ammeter (A). In our first MOSFET circuit that will be built, we will substitute a potentiometer for the variable voltage source, and a light bulb for the ammeter (load).

Before you build your circuit, or even pick up your first MOSFET, make sure to understand ESD precautions, because you can destroy your first MOSFET just by walking across a carpet, building up static on your body and clothing, and touching the gate terminal of the device.

3.2 Special Insert – ESD Safety First

The resistor from gate to source is an ESD protection measure. Install it in the circuit first. Install the MOSFET last. That resistor works in the cases where an input voltage source is not connected, fails, or a wire gets disconnected (on a breadboard, for example). In those cases, if that resistor was not connected, the MOSFET turn ON and OFF sporadically, simply because of noise on the gate terminal. Even touching the terminal with a finger will be enough to turn the MOSFET ON.

A more serious condition results if your body an clothing has collected a static charge, and the MOSFET gate terminal is touched. If you have walked across carpet, or moved around in a chair, your body and clothing have generated a static charge. If you did not wear an ESD grounding strap, and were not using an ESD table mat, then touching the gate terminal would destroy the MOSFET with the charge discharging thru the gate terminal.

To install a MOSFET into a circuit, discharge yourself first (if you do not want to buy an ESD setup, then touch a grounded metallic part, such as uninsulated back of your desktop tower, or a wire connected to the hot water heating system). Then, install without touching any leads.

Place or keep ESD foam on the device when bending pins or removing from bag. Install ESD gate resistor on the breadboard first. Use ESD discharging equipment, and install MOSFET immediately after taking off ESD foam. Save the ESD foam. If you do not have ESD foam, then use a small piece of aluminum foil.

MOSFETs are very sensitive to static electricity. Any small electrical discharge can create an unwanted conduction (turning of the device ON).

Always transport an electronic device in an ESD bag (or with ESD foam installed).

Always wear a static strap when handling MOSFETS.

ESD preventing mat and wrist strap kit. 276-2370, $27

Fig 3.3

This will be our first MOSFET circuit. A light bulb is used as a load, but it can be a relay, a motor, a power resistor, etc.

R1 is a potentiometer which will supply a variable voltage level to the Gate, in the range of 0V...VDD. In this circuit, MOSFET gate does not require any significant current, just a voltage level. R1 therefore can be of any value over 1k (to minimize power dissipation), up to 47k. The upper range of that resistance (47k) will be limited by gate protection circuitry which we will introduce shortly.

Fig 3.4 BOM

Table above is a BOM, Bill of Materials, listing part numbers for a circuit diagram which you have seen earlier. It is not necessary to buy all of the parts in the bottom section, nor is it needed to buy exact parts specified. Use whatever is available and affordable. In the top section, 5k pot can be any 1k-47k part which you already have (or get one from a scrap board).

Also, obtain the full IRF510 datasheet at http://www.MKRD.info/SemiconductorsBook or http://wiki.mkrd.info/RadioShack_Transistors_Datasheets

Note: RadioShack heatsink which I listed is not adequate for a prolonged period of operation or high duty %. That heatsink also requires you to purchase heatsink paste (grease), a 4-40 bolt, compression washer, and a nut (which are cheaper at a hardware store) separately.

Build the circuit. I recommend soldering wires to the adjustable resistor, and plugging those wires into the breadboard. If you can, adjust the potentiometer so that its wiper is closest to the lower terminal in circuit (0V), so that MOSFET will be off when you connect the power supply. Connect one of the loads in the circuit (#1).

Before you switch loads from one to another, always disconnect the power supply, turn the potentiometer in the position that has it turn OFF the MOSFET (wiper closest to the 0V lower terminal in the circuit), connect another load, and only then reconnect the power supply.

Turn on the power supply last, after all of the connections are made. Rotate the potentiometer slowly, and see what happens. Record what you can measure with your DMM in this circuit, in your lab notebook. Record all observations and preliminary conclusions in your lab notebook.

Experimental Findings for a circuit with an IRF510, 8Ω power resistor, and a 12V power supply. By adjusting the potentiometer, we find:

Almost no drain current flows without control voltage, positive with respect to source (VGS=0V). Taking a precise measurement, 0.12mA current flows at VGS=0V. Curiously, the datasheet specifies a much smaller value, but RadioShack device data matches this finding.

No drain current flows until a certain control voltage level is reached at the gate. With RL=8Ω, VSS=12V, my circuit was showing this value to be 2.6V. This value will be somewhat different between different MOSFET part numbers, and a little different between devices of the same part number. If you look into your MOSFET datasheet, this value will be approximately equal to the VTH (or VGS(th)) specification.

Maximum current for our load (does not increase any further) flows at about VGS=6V. At VGS=6V, current flowing thru the load is almost the same as if the MOSFET was a short between drain and source (IL ≈ VSS / RL).

Repeating the measurements with a halogen bulb, I got: 3V VGS to start current, 6V max current flows. 1.75 A current flows. And the MOSFET effectively looks like a 0.9V VDS drop.

See if you can plot ID (by inserting a DMM in current measuring mode between the MOSFET+diode anode point in circuit, and the lower terminal of the load in circuit). Plot that vs. VGS measurements which you can take with a second DMM (or by switching one DMM from current to voltage measurements), over half a dozen points. Alternatively, you can make a rough sketch based on your visual observation.

The plot you get of ID vs. VGS should look like:

Fig 3.5

Notice that the VGS vs. ID relationship is not linear, but is quadratic. This plot is only valid for the active region of operation (we will find out what that means in a bit).

Almost all datasheets show a log-linear plot instead. It is important to remember the plot above as the intuitive model of MOSFET operation. Any plot other than a linear-linear one is a tweaking of the numbers. A log-linear plot is created because it allows easier extraction of measurement points, or, more importantly, to compress the plot over several decades (powers of ten) changes of parameters. For example, notice that in the plot above, a very small portion of drain current is shown, for a change of only a few milliamps. Notice also that it is hard to take precise measurements along the plot even in this small range.

Here is an example of a typical log-lin plot from a datasheet:

Fig 3.6

Note that the plot gives values over a huge range of drain currents, from 0.06A to 11A. This is helpful, but for measurements only. To extract an intuitive grasp of MOSFET operation, the plot would have to be mathematically converted to lin-lin form.

We have learned a few things about MOSFETs already.

When VGS < VTH, MOSFET is in a mode of operation which is called “cutoff”. MOSFET is turned off, and no ID current flows.

We will study other modes of operation (when current is supplied to the load) shortly.

Let us now study IRF510 datasheet. We are given a drawing first,

Fig 3.7

On the right is the standard symbol for an N-channel power MOSFET. All those things in the drawing are indicative of the device's physical construction and its operation. This book will not go into details of how MOSFETS are actually made.

Note the diode between source and drain. Recall that it was previously noted that the drain must be more positive than source. If the MOSFET was connected “upside down” in the previous circuit, with ground at drain, and load connection at the source, then that internal diode would uncontrollably conduct full current (device would behave as a diode in forward operation). For the safety of the device, power MOSFETs cannot be operated in such a way (device destruction will result).

To remember how to connect a MOSFET correctly, note that the device is to be connected so that drain to source current flows in a direction opposite to the symbol arrow and the diode.

Returning to the datasheet we see “Absolute Maximum Ratings”. This is self-explanatory. Operation beyond these ratings will result in device destruction. Most ratings listed are similar to diode ratings which you already know.

VDSmax: maximum circuit power supply voltage

VGSmax: maximum controlling voltage which can be applied to the gate

IDmax: maximum current which the device can supply to the load

PDmax: maximum power which the device will dissipate, due to I2*R losses in the device

The next datasheet section, “Electrical characteristics”, describes parameters of a device operating below the maximum specifications.

VTH or VGS(th): Threshold voltage which we have already seen in action. A MOSFET does not start to pass any current until this value is exceeded. Note the range indicated: 2 to 4 Volts. This is an indication that MOSFET devices will be different from each other, and a circuit designer cannot assume an exact particular value for threshold voltage.

RDS(on): resistance which the device presents in circuit when a high enough gate voltage is applied. At this gate voltage level, MOSFET is fully “open” to current flow thru itself. It will only present a small series resistance, which is specified in the datasheet. We have already confirmed experimentally that the MOSFET, with a high gate voltage applied, supplies nearly the full current to the load, as if it was a short from drain to source.

Let us now examine that VGS = 2.6V to 6V region of operation in much more detail.

We have already discovered the “cutoff” mode of MOSFET operation – at VGS < VTH, ID = 0.

Another “region of operation” would be breakdown – whenever any of the datasheet maximum specs are exceeded (such as VDSmax, VGSmax, Tjmax, etc). You only see a MOSFET operate in this region once in its lifetime – because magic blue smoke escapes, and your device does not want to operate anymore.

There are two more modes of MOSFET operation. Be forewarned – thorough understanding of principles in this section is required to design proper circuits. One of main reasons behind the writing of this book were the confusing, unintuitive, complicated, and incomplete explanations of MOSFET operation found elsewhere. Do not proceed further with MOSFETs before you understand concepts in this section. I will succeed if I will make the learning process painless.

In that VGS = 2.6V to 6V region of operation, MOSFET is somewhere between being fully closed (ID = 0 at VGS < 2.6V), and fully open (ID = max at VGS ≥ 6V).

If we take several measurements from the previous circuit, a graph like the following will result:

Fig 3.8 ID vs. VGS graph. Log-lin (left), lin-lin (right).

For the left plot, note that VDS does not change, but it is steady at 50V. Note also that ID y-axis is a log plot, displaying powers of ten. That axis, therefore, goes from about 0.1A to 10A (three orders of magnitude). How close is this plot to our experimental setup? Does our VDS vary with increasing current to the load (measure it)?. Do we start our measurement at 0.1A and VGS=4V? Do any of our loads draw 10A of current? Can our MOSFET supply 10A of ID current for an extended amount of time? That plot is valid only for a single 20 microsecond pulse.

There is a lesson to be learned. Do not rely on datasheet specs for an exact match to real circuit performance. Note also that the plot does not take into account VTH variability, which is a 2V spread for this particular MOSFET. The plot on the left can have the x-axis values shift by 1V left or right. Don't take precise measurements from the plot as given!

We can, however, extract qualitative observations from this plot, and see if they match our own experimental observations.

The main observation is the large change in ID – x56 increase for a 3.75V VGS change. Does this match your circuit? Do currents shown match currents your load receives if you supply your MOSFET with the VGS voltages given?

We can find from the plot or our own calculations that the drain current, ID, is proportional to (VGS-VTH)2.

Active Region of Operation

There is a scary looking plot in the datasheet, and in all other textbooks. It is a very confusing plot, and one that is hard to understand. No wonder, since four changing variables are plotted at the same time. We will take the plot step by step.

Firstly, build another circuit. This time, we want to be able to change VDD (power supply voltage), and be able to set VGS independently of those changes. We will need to use two power supplies – one adjustable, the other one fixed. For the fixed source, any wall-wart unit supplying 9...18V will do for this MOSFET. Just make sure to measure wall-wart voltage, so that it does not exceed VGSmax without a load. Unregulated wall-wart power supplies supply several volts higher than their spec without any load attached. Our 5k pot plus the MOSFET gate will not load the power supply appreciably. Resistance of the pot is not critical. It can be in the range of 500Ω to 10k.

Fig 3.9 Now use MOSFET symbol

Make sure to rotate the pot to the bottom position, with the wiper at 0V terminal, before connecting the load and the power supplies. Set the main power supply to 12V. Turn both supplies on. Rotate the pot slowly to set a relatively low current in the load. If you are using a light bulb as a visual load, set its brightness to a very low setting (50mA or so). We are not going to adjust VGS for now, but hold it steady.

Now adjust the main power supply in the range of 5-25V. If your power supply displays current draw, watch that it does not exceed the light bulb's stated current draw. Does ID change by a lot with VDD changes? Can you increase VDD to 20V without exceeding the light bulb's current rating? Measure voltage across the bulb at that point, as well as at a much lesser VDD value (5V). What do you see?

With a careful setup and plenty of notes, you should have noticed that VDD variations had a very small effect. You could have varied VDD by as much as 5V without significant ID changes if VGS was held constant.

Note that VDS is different from VDD because of the voltage drop across the load.

We call this relationship “Active mode” of operation. In active mode, drain current is controlled by gate voltage, and is proportional to (VGS-VTH)2. A MOSFET is in “active mode” as long as

VTH < VGS < (VDS+VTH)

and VDS is at least several volts. In this region,

Since we had a device with VTH = 2...4V, and we had connected it to a power supply voltage of 12V, while varying gate voltage at 0...12V, our circuit satisfied “active mode” criteria.

It is time to introduce some scary-looking plots. MOSFET is a device which has its behavior set by several parameters which can change in a circuit. In general, MOSFETs behave like so:

Fig. 3.10.

This qualitative plot shows a great deal of information. On the vertical axis is the ID, current which is supplied to the load. On the horizontal axis is the VDS, drain to source voltage (drop across the MOSFET). This is, as you should have already found, different from VDD, power supply voltage. Unlike VDD, VDS varies with VGS, and decreases as more current is supplied to the load. The three dashed lines on the plot are limitations which we have already discussed. There's the breakdown limit of 100V. There is also the Active Mode constraint (vertical line). And the horizontal VTH line shows the cutoff voltage VGS < VTH.

We have, however, a third variable – VGS. I have shown a plot with VGS set at one particular value – VGS does not change, but is held constant for the plot shown.

At a later time, we will see that this plot is actually valid for many different VGS values. All that needs to be done to get a plot of at a different VGS value is to move the curve shown up or down the plot. Arrows with ± next to the VGS line show that VGS can be varied, and so will the plot. Generally, increasing VGS will move the line up, while preserving its shape, and moving VGS down towards 0V will move the line down. As we already know, dropping VGS to VTH will make ID=0. For now, we will concentrate on just one fixed arbitrary VGS value.

To analyze this plot, you can mentally keep one variable fixed (VGS, for example), change the second variable (move along VDS, for example), and read off the resulting value off the third variable (to see what happens to ID if VGS is fixed, but VDS varies, for example).

We will examine the shape (slope) of the plot first. We see that it increases rapidly, and then levels off. In the “level” area of the plot, we can see that at a certain value of VGS (as shown), changing VDS does not affect ID by much. We have seen this behavior already! This is the “active” region of the plot.

In active region, ID is set by VGS, and is not dependent on VDS changes.

The benefit of the active region is MOSFET circuit predictability. Changes in VGS (circuit input) would produce predictable ID changes. As I have mentioned, ID is proportional to (VGS-VTH)2, which means that the equation looks like

, where k is a constant.

Fig 3.11

As the MOSFET is producing those ID changes, it would open or close proportionately. As it does so, it will drop varying amounts of voltage VDS across itself, as shown in Fig 3.11. In the “active” mode of operation, MOSFET drain current is not affected by VDS (or VL output) voltage. A circuit which changes behavior based on both input and its own output behavior is useless for many applications. It would not make a linear circuit such as an audio amplifier, for example. Tricks to ensure a MOSFET circuit stays in active mode of operation across the whole range of allowable input levels will be discussed in the JFET and BJT chapters. This chapter will only examine MOSFETs in switching circuits, and we will be allowed to not keep to the predicable “active” mode of operation.

Do not think that “active mode” is an exact boundary. Instead, modes of operation switch over from one mode to another gradually. You can see the boundary in Fig 3.10, in the portion of the plot close to the origin.

Brief note: almost all other sources also call MOSFET “active” mode as “saturation” mode. This will conflict with our treatment of BJT behavior in one of the next chapters. In order to eliminate confusion, this mode of MOSFET operation shall be called “active” mode.

3.3 Ohmic mode

Remember those four changing variables which I have mentioned the Fig 3.10 plot shows?

Fig 3.12

The fourth variable is the slope behavior of the plot. In “active” mode, VGS plot was flat, so that changes along the horizontal VDS axis did not produce large changes on the ID axis. However, a different behavior appears when VDS is lower than two volts or so.

We now have a new qualitative plot which is simultaneously showing MOSFET behavior over several VGS levels. This new plot is a re-examination of Fig 3.10, at low VDS values. At this area of the Fig 3.12 plot, increasing VGS any further will no longer increase ID accordingly. Very small increase in ID results from increasing VGS.

To examine this plot, we now hold ID constant, as we are usually interested in a circuit that can set this to a specific value, and hold it there. We then vary another variable – VGS in this case, and see what happens to the third variable, VDS.

Looking at the plot from this angle of approach, we see that at an ID of “needed value”, VDS can be decreased even further by increasing VGS even higher, at any point on one of the plots above. Place a mental horizontal line at an ID of a needed value. One of the VGS plots will intersect this line at a specific VDS value. What if you needed an intersect at a lower VDS value? One of the dashed plots (at even higher VGS levels) intersects the horizontal ID line at the lower VDS level.

I have placed bold dots on curves of several VGS values. They all read the same ID value. What does change, however, is the value of VDS. It seems like the MOSFET is opening up even further, since it is decreasing VDS voltage drop across itself as VGS is raised, but it is not increasing ID thru itself.

This “ohmic” region of operation is used for two purposes. One purpose of this mode of operation is in circuits where a small VDS drop is needed. Switching circuits which behave like a mechanical relay benefit from small VDS drops.

Why is this mode of operation called ohmic? Because a MOSFET is commonly looked at as a voltage-controlled current source. It acts like such a device in the active mode of operation, where ID is directly related to VGS level. However, ID increases little in the ohmic region of operation. VGS mostly affects VDS. At a nearly constant drain current ID, decreasing VDS behaves like a decreasing drain-to-source resistance of . It is even possible to build a voltage-controlled resistor with a MOSFET in this region of operation (second purpose of this mode of operation). However, we are only interested in the MOSFET as a switch in this chapter, where an application of a control voltage VGS causes the MOSFET to open up to a large current flow with a minimum voltage drop across itself, much like a mechanical relay.

Minimum achievable VDS

Remember one of the core lessons of the book: do not be mesmerized by datasheet plots or cute equations. In reality, our MOSFET cannot approach a useful VDS=0, at the rapid drop-off portion of the plot. Why? Because we have RDS(on), and there is a minimal VDS which is a product of RON and ID(max) (VDS(min)=RDS(on)*ID(max)). See what that value is for high power loads which we have used. I got about 0.9V.

MOSFET as a switch

Back to our experimental findings. If you have made good experiments, and made good observations, you have noticed that while increasing VGS above VTH quickly got a lot of current flowing thru the load, increasing VGS even further would result in small additional ID increase. Verify this behavior, and plot VDS vs. VGS. You will produce a plot similar to this one:

Fig 3.13

Although I have asked for a VDS vs VGS plot, the one commonly shown in datasheets is a RON vs VGS plot. The two plots are closely related, since ID does not increase by much in ohmic mode.

Increasing VGS will result in the MOSFET decreasing the voltage drop across itself, as well as its resistance. Even larger VGS will drive RDS(on) even lower. Which VGS drive voltage should we apply if we want the MOSFET open? Since a lower RON and VDS means a smaller power dissipation, then a high enough voltage should be applied, for the lowest possible RON. Note however that RON decrease slows down after a high value of VGS is exceeded. At even higher VGS, RON decreases very little. The part of the plot where RON becomes horizontal is a good choice of VGS, however, do not forget that these plots can be off to the right or the left by as much as two volts due to VTH variation. Also do not forget the VGS(max) limit.

Voltage requirements

Regions of operation are not exact boundaries, so the following are general requirements for ohmic mode of operation:

To enter ohmic mode, VDS should drop below a couple of volts. The formula is

VDS < (VGS – VTH) or VGS > (VDS+VTH)

With an additional condition of VGS>VTH, of course.

These equations are just for the reader's reference. We will never depend on cute equations like these because neither our circuit conditions nor device characteristics are known precise enough to depend on equations. VTH varies by several volts for different devices of the same part number, for example. A more meaningful task is to design a circuit which will not violate these boundaries no matter what the operating conditions (such as temperature) or device variability is encountered.

3.7 P-Channel MOSFET

There are times when a circuit designer needs a device which will operate with different input or output polarities.

Let us mentally recall our switch circuits presented so far. We had a load, one terminal of which was permanently connected to VDD, and a second terminal voltage at which was changed anywhere from VDD voltage level down to 0V voltage level.

We also had an input, which caused no current to flow when input voltage was 0V, and a large current to flow when it was at a higher level.

There are instances where either the load must have one terminal always attached to 0V, or a circuit must allow no current at a high input voltage, but allow more current as input voltage drops towards 0V.

For instances such as these, there is a second type of a MOSFET: a P-channel device.

Fig. 3.14 P-channel

Note the arrow in the middle pointing in the opposite way when compared to the N-channel MOSFET which we have already studied.

Regarding necessary voltages for operation, for a P-channel MOSFET:

1. Source must be more positive than drain

2. A negative voltage must be applied to the gate to control the device

3. Gate voltage must swing from voltage at the source to the voltage level at the drain to turn the device ON

I have worded property #2 purposefully as confusing as other textbooks do, in order to explain it. There is no need to wonder how to obtain negative control voltage to turn on a P-channel MOSFET. Whenever a voltage is specified, it is always relative to a common point in a circuit. In most cases, that point is the 0V common, aka negative terminal of the battery, VSS, or COM.

We can easily satisfy the necessary voltages criteria by flipping a P-channel MOSFET upside down, and connecting its source to the VDD (highest voltage point in the circuit):

Fig 3.18

You can also use the same potentiometer as before to control this circuit.

Fig 3.15

And this circuit can be used to control a MOSFET from digital logic or a microcontroller. Note that we must still connect an ESD protection resistor to COM. Since this resistor will pull the gate down, potentially turning the MOSFET on, we must also use a pullup resistor to pull the gate up, overriding the ESD resistor of higher resistance value, if we want our MOSFET to be OFF without an input connected.

As far as all other datasheet parameters go, they are still the same as for an N-channel MOSFET, except that VDS and VGS polarities are reversed. View a datasheet of a P-channel MOSFET to see for yourself.

The following is an illustration of a common P-channel MOSFET application – a "low dropout power supply switch”. All the MOSFET does here is supplying full power supply voltage, as close to the rail as possible, without appearing as a resistor of a relatively large value.

Fig 3.16

Inverted MOSFET gate drive limitations at high voltage

Notice that gate voltage must be at power supply voltage for the MOSFET to be OFF, and it must swing towards circuit Common to turn the MOSFET ON. Gate driving circuitry must be capable of outputting a gate voltage equal to power supply voltage. If the MOSFET is being driven from a high-voltage power supply, then a logic chip would not be able to operate at that voltage.

Notice also that with a high power supply voltage, voltage VGS (max) cannot be exceeded when the gate swings towards COM. If VGS (max) is ±10V, then a circuit such as Fig 3.19 is not capable of 12V operation. A specialized circuit or driver IC must be used instead.

In chapter 7, there will be an in-depth discussion of possible methods of driving MOSFETs in this configuration.

We will not pay too much attention to P-channel MOSFETs – due to the way they are made, a P-channel MOSFET is usually worse in its parameters than an N-channel MOSFET. Their VTH and RDS(on) are higher, VGS, ID(max) and VDS limits are lower, and switching speed is less. Fewer of them are made, as well, resulting in lesser parameters and cost choice. However, a search on a parts distributor's website will uncover P-channel devices which are on par with N-channel devices on most parameters, including cost, because several manufacturers have renewed their interest in actually manufacturing the devices.

In everything else, P-channel MOSFET operation, expect for the inverted voltages, is the same as that of N-channel.

3.8 MOSFETs in digital logic

Our modern world has been enabled by digital technology. By simplifying everything down to only two voltage values: HIGH and LOW, several benefits have been obtained:

Error-free storage, processing, and reproduction of information

Error-free communication

Highly predictable circuit operation, which can be described in exact terms

and many other benefits

From the standpoint of a circuit, the input looks something like:

Fig 3.17 Digital signal stream

For an ideal digital signal, the following conditions must be met:

Only two voltage levels are allowed, HIGH and LOW

The signal can switch between the two levels, but only instantaneously. The signal must not spend any time in intermediate voltage levels. As we will see later, this not only eliminates uncertainty in interpreting the digital signal, but also minimizes heat generation in the circuit.

Logic output should swing all the way to VDD for a logic HIGH, and all the way to 0V for a LOW. This minimizes heat generation, minimizes uncertainty, and maximizes logic drive capability (how much current can be supplied if many digital logic inputs were connected to that one digital output).

Real-life digital logic such as the CMOS family may have specifications such as the following:

Logic HIGH: 3.5...5V where the lower voltage is the worst value, and the higher one being desirable.

Logic LOW: 0...1.5V where the higher voltage is the worst value, and the lower one being desirable.

VDD: 5V typical, but can be higher.

For logic output, what we would like to have is:

Fig 3.18

We have discovered two MOSFET types. We can arrange them in a unique way to implement this circuit:

Fig 3.19 CMOS with 2 MOSFETs

This is called CMOS logic; C stands for complementary and MOS stands for MOSFETs.

When the input is LOW, P-channel MOSFET on top will source current to the load. When the input is HIGH, the bottom N-channel MOSFET will sink current from output into COM.

With input being either LOW or HIGH, this circuit ideally would not produce any heat and wasted power. It will act like a mechanical switch.

There is, however, an intermediate range of voltages between an input value of HIGH and LOW at which neither of the MOSFETs will be fully on. Therefore, they will not supply a voltage swing all the way up to VDD (HIGH) or 0V (LOW). They will also not supply full current to the load. While supplying current, because RON will not be optimally low, one of the MOSFETs will also generate heat due to I*R losses.

Even worse, both MOSFETs will be somewhat open at an intermediate voltage, shorting VDD to COM thru themselves! This will generate unacceptable loading of the power supply and heat generation within the device.

This is the reason why no intermediate voltages are allowed in digital logic, and why digital switching between HIGH and LOW should be as fast as possible (no slow transitions, but square wave input instead). Just like our switch, the circuit should not spend any time in the “in-between” gate drive voltage levels.

About the worst input voltage level that can be supplied to a digital logic chip is a halfway value between HIGH and LOW bounds (often, ½ VDD). Logic switching will consume power in the in-between voltages:

Fig 3.20

Build the circuit, and see for yourself how well it operates. There are specialized devices or ICs available which contain both MOSFET types in one package, and with matched parameters. To explore the category, look at Digi-Key's Discrete Semiconductor Products : FETs – Arrays : N and P-channel.

Fig 3.21 Package with 4 gates

Another THING NOT TO DO with digital logic is leaving input pins unconnected. It is easy to make the mistake, if you have a 14 pin DIP package with several gates, but you are not utilizing all of them.

Any CMOS digital inputs which are not used must be tied to VDD or COM with a resistor of a 10-100k value or so.

Since a MOSFET does not require any appreciable current thru the gate to turn on, an unconnected pin will be "floating" at any value. Any noise or leakage will lead to a voltage level at an input, which will be turning MOSFETs in the gate on and off. A floating input will result in MOSFETs which are either both slightly open, or rapidly oscillating between HIGH and LOW output. A gate behaving like this will load the power supply, overheat, and affect other gates in the circuit (thermally, by injecting noise, and by dragging down the power supply).

Discrete MOSFETs can be used in digital logic for simple applications where using a separate chip would take up board space, use more power supply current, etc. Typical discrete MOSFETs in logic applications include: buffer (isolate one circuit from another), driver (drive a load with more current than a logic gate can produce, and protect a gate from other factors of driving the load), digital—analog interface, etc.

We will look at an inverter first.

Fig 3.22

Now we will look at a digital to analog interface. There may be a need for a digital output voltage level to be converted to a transistor drive level (higher voltage or higher current), or for an output to control another part of the circuit, by clamping it down perhaps, where rail to rail swings and moderate current drive capability of CMOS is not required.

Circuit below will use a MOSFET to clamp down an input to another gate. We have a 1k pullup resistor which will normally supply a logic HIGH to the circuit, but a fully open MOSFET will override the resistor and pull the input to LOW. No significant currents were needed in this case.

Fig 3.23 Discrete MOSFET digital logic application

Low power supply voltages

What happens if we operate a circuit with a much lower power supply voltage? There are two factors to keep track of.

Firstly, VTH is a parameter which starts to have an effect at low VDD voltages. For a conventional MOSFET gate, VTH of 2...4V are typical. For such a MOSFET, operation with the gate tied to 5V VDD will not result in a large drain current.

VTH can be lowered if a “logic level gate” MOSFET is used instead. VTH in those MOSFETs is made as low as possible, usually 1...2V. Keep in mind that VGSmax usually decreases as well as a tradeoff.

Secondly, VDS due to load voltage drop starts to approach ohmic mode of MOSFET operation. As we have seen before, at small VDS values, ID becomes dependent on VDS value. This is not acceptable for linear circuits operating in the active region of operation, but is OK for switches operating in the ohmic mode.

However, at very low power supply voltages, to ensure enough drain current flow and a low ON resistance, a gate voltage above power supply voltage is required.

3.9 MOSFET as a high-power switch

How can we find what level of VGS drive voltage is necessary to conduct a certain level of current?

We go back to the datasheet, and examine two plots which are given to us, where several regions can be viewed at the same time from the "family curve".

Fig 3.24

I have plotted our givens. If we are to use a RadioShack part number 12V 20W halogen bulb as a load, our maximum load current would be 1.67A. Keep in mind that axes on the graphs below are log based (100=1, 101=10, and so on).

I have plotted results for several types of loads. Make your own table.

Fig 3.25

How well does this compare with the datasheet? As you can see, datasheet and our experimental findings do not exactly agree. However, recall that the threshold voltage was given to us to be 2...4V, and that he transfer characteristics of the datasheet are said to be “typical”.

As a circuit designer, you have to plan for the worst device behavior, to ensure that your circuit still function as it should. For an IRF510 circuit, assume VTH of 4V, and apply a sufficient gate voltage which will ensure maximum current flow thru the load. For our loads of the relay, 14V bulb, and the motor, applying at least 5V to the gate will ensure maximum current.

There is an equation which you'll see elsewhere which allows a calculation for drain current from a value of VGS. That equation requires a constant which is determined by measuring the drain current at two other VGS values. If this sounds unreliable and pointless, well, it is. Remember that all plots in a datasheet are “typical”. That plot may be off a few volts up or down. Do not get a false sense of precision from cure datasheet plots and equations found elsewhere.

3.6 MOSFET as a low power switch

Before we head off any further into high power applications, we should finish our coverage of low-power circuits.

We do not use a beast as large as an IRF510 (with a heatsink attached) for low power. MOSFETs are also available in TO-92 and DIP packages (more variety is available for SMD parts, of course). I have an article on selecting thru-hole low-power MOSFETs on my website.

In a low-voltage circuit a MOSFET such as IRLD024 (ID=2.5A) or a ZVN4206AV (ID=0.6A) with have a threshold voltage of 2V (first device) or 3V (second device). Gate voltage which will allow a high enough drain current to flow may be around 3V (first one), or 5V (second one). These are ideal for 5V logic and microcontroller applications.

For variety, we are now turning the MOSFET on and off with a switch instead of a potentiometer.

Fig 3.26

RON becomes a factor if a low power MOSFET is used. Low power MOSFETs do not have a RON anywhere near as low as high-power TO-220 package power MOSFETS with RON of <1Ω. Small power MOSFET RON is 1Ω (best devices) and higher (which implies that small power MOSFETs cannot supply a very large current by swinging their drain almost all the way to the source).

For an example of thru-hole devices with good parameters, in a low-voltage circuit a MOSFET such as IRLD024 or a ZVN4206AV with have a threshold voltage of 2V (first device) or 3V (second device). Gate voltage which will allow a high enough drain current to flow may be around 3V (first one) or 5V (second one).

Driving high power MOSFETs

Let us examine in more detail the operation of our circuit when it switches high-power loads.

Looking at the Fig 3.25 table (or the datasheet), we see that we need at least 6.5V to supply maximum current to a halogen bulb load.

Fig 3.27

What if you needed to drive such a high-current load from a digital logic output, which only goes to +5V? As an example, we could have a Parallax Basic Stamp module driving the MOSFET. Basic Stamp outputs can only do two things: connect the output to +5V, or connect the output to COM.

Fig 3.28 Driving high power MOSFET with digital logic.

We just use a trick – connect a pullup resistor from Basic Stamp output to a supply voltage!

Note: not all logic allows the output to be pulled above its own power supply level. Some logic outputs use output protection diodes which start conducting if the output is pulled to high voltage. Unless you are sure the logic chip you are using can tolerate this condition, do not implement this solution without an isolating buffer (more on this in the rest of the book).

Let us examine the circuit at length. It contains a lot of components, but we will examine it step-by-step.

A Basic Stamp controller board consists of three major components: a 9V battery, a regulator which converts 9V to 5V, and a Basic Stamp controller, which can, depending on what it is programmed to do, swing its output to either +5V or COM (0V). In our circuit, the entire Basic Stamp controller is simplified to a black-box triangle, which shows its essential functions. Only three connections are made to the triangle in our simplistic circuit.

The circuit in Fig 3.28 allows you to have a MOSFET “high-power” circuit either on the Basic Stamp controller breadboard, or a completely separate board (represented by vertical dash lines). If you have your MOSFET on a separate power board, remember to connect your MOSFET's COM to your Basic Stamp's COM, just like the circuit shows. If you don't, the circuit will not operate.

You have another choice with this circuit: to feed the MOSFET circuit from the on-board 9V battery, or use a separate high-power power supply. Using an on-board 9V battery is fine as long as the LOAD does not require a higher voltage and a high current, but will drain the battery quicker than having it run just the Basic Stamp.

And a third choice that you will have is which power supply to connect the pull-up resistor RP to. If you only use the on-board battery, you will connect point A to point B (even though this will be of little use, as the on-board 9V battery will not be able to supply a large enough current to a LOAD to need a VGS any more than 5V). If you use an external power supply, you can connect it to either B or C, as both power supplies are of high enough level to drive the gate high enough. Just make sure that the supply you are connecting your pullup resistor to is not ≥VGSmax.

Alternatively, you can use a logic-level gate MOSFET. These MOSFETs are made with much lower VTH ratings (1...2V typical), and will open fully at logic HIGH levels (5V typical). However, watch out that VGS(max) will be lower. IRL510, a logic-level gate equivalent of IRF510 has VGS(max) of 10V. Logic level MOSFETs have a much lower VGS limit than a common MOSFET.

Also keep in mind that even an ordinary IRF510 can pass plenty of current at VGS = 5V. Assuming a digital output HIGH swings to within 0.5V or VDD of 5V (a good assumption), we see that our MOSFET can control a 300mA load. This is plenty for many applications. However, we have seen before that even though a MOSFET may turn on at low or logic level drain supply, RDS(on) will continue to decrease with increasing VGS.

MOSFET drivers

In many instances, driving a power MOSFET directly from a logic output is not a good idea, especially when we get to the next section on high-speed driving. We need a driver in those instances. The requirements for a driver are:

Swing gate voltages to sufficient levels (most often, higher than 5V HIGH)

Supply enough drive current (more on this in the next section)

Switch fast, without spending time in intermediate voltages

Do not load its input (previous logic gate output) appreciably. Therefore, isolate the power MOSFET from digital gate output.

Tolerate all the nasty things which a switching MOSFET will subject its driver to: high current to switch gate capacitor quickly, current being forced back into the driver output, noise/pulsing on the power supply lines, ability to be connected to a high enough power supply voltage to turn on a MOSFET fully, and so on.

For medium-power MOSFETs, these requirements can be met with a low-power MOSFET (or another transistor type, more on this in the next chapter), a digital buffer, or a specialized driver IC.

Fig 3.29 Driving power MOSFET from 5V logic

Logic output, a logic buffer, or a discrete circuit would not suffice for driving high power or high voltage MOSFETs. Attempting to drive a high power MOSFET from digital logic may result in: a) slow switching, b) microcontroller resets due to power supply and output current spikes, b) damage to digital logic / microcontroller due to over-current on the output. A specialized IC driver should be used.

If you want to see what is available among specialized driver ICs, look at the accompanying collection of datasheets for this book, or explore Digi-Key's category – Integrated Circuits (ICs) : PMIC - MOSFET, Bridge Drivers - External Switch : Low-Side

Gate resistor value and MOFET failure modes

Why is a gate resistor used, and what should its value be? Although we will not be able to answer this question fully until the next section on high-speed switching, there is a role for that resistor in this section as well.

A common MOSFET failure mode (from ESD, driving inductive loads, etc) is for every terminal to become shorted to every other terminal, or become low resistances. Gate in this instance will become connected to COM, and will short logic output to COM. Digital logic has very low current source or sink capability (20mA typical). A gate resistor of a value larger than 250Ω will ensure that a logic gate survives such a scenario. A value of 470Ω or more is recommended.

If a driver with a higher current capability is used, adjust the resistor accordingly. Nevertheless, a MOSFET which has been destroyed commonly takes out the driver IC as well. When replacing a bad MOSFET, do not connect power to circuit until you verify the driver IC as well (there should not be a low resistance from chip's VDD to COM pins, or from driver output to either of the two power supply connections).

An even more important reason to have a gate resistor will be discussed in a next section on high—speed switching.

Additional factors of high-power switching

Temperature effects

We had to mount our MOSFET on a heatsink, and if you have tried connecting high-power loads to your circuit, you found out that the heatsink gets hot! Why?

Fig 3.30 Equivalent circuit for dissipation calculation

Because the MOSFET can be thought of as a variable resistor.

Resistor on top is the resistance of the load. For example, a 12V 20W halogen light bulb is an effective resistor with the value of of 7.2Ω. Note: for a light bulb, this is only true when it is warm. A light bulb which is just turning on will show a much lower resistance. Measure it yourself with a DMM. My cold-filament measurement was 0.5Ω.

Resistor on the bottom is the lowest possible “on” resistance of the MOSFET, with a high enough voltage applied to the gate. It is listed in the datasheet as RDS(on) of 0.54Ω. Then you notice the asterisk. “b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %.”. It is also dependent on temperature, as Fig. 4 of the datasheet shows (more on this later). Their measurement of 0.54Ω was taken at a temperature of -50 °C. That would be an applicative temperature only for my North and South Pole readers. At a more reasonable temperature of a warm MOSFET in a room temperature environment, perhaps 30°C, and at a maximum continuous drain current, RDS is a more realistic 1Ω. An experiment to measure it with a 12V 20W halogen bulb load gave me a reading for a 0.9V drop across the MOSFET. Find the equivalent MOSFET resistance if it dropped 0.9V.

Variable resistor in the middle is the “mode of operation” of the MOSFET. That resistor can go from a very low value to a very high value.

Power dissipation can be found by applying Ohm's law to every resistor.

At very high MOSFET resistance, RM is very high. ID is very low. There is effectively no power dissipated in either the MOSFET or the load.

When the MOSFET is fully open, ID will be 5A, RM may be 1Ω (typical value for an IRF510 at this current).

With a 20W halogen load, my measured voltage drop was 0.8V. This is a better-than-typical performance. A typical power dissipation for an IRF510 with a halogen bulb as a load will then be . Such an amount of dissipated power requires a heatsink.

Calculations above were for a completely OFF or a completely ON MOSFET. What about a partially open MOSFET? What if it was open only enough to supply 6V to the bulb?

At 6V, our bulb will be a 7.2Ω resistor. ID will be .

In order to supply only 6V to the bulb, our MOSFET will have to become a resistor with a value of . What we have is a basic two-resistor voltage divider. How about power dissipation?

Our bulb will produce of a mixture of 70% heat and 30% light (typical efficiency).

Our MOSFET will have to dissipate thru the heatsink .

This is the same as the bulb! To illuminate a bulb with 5W of power, the only thing our MOSFET can do is dissipate the rest in itself, in the form of heat. That will only be a 50% energy efficiency in delivering power to the load.

For all semiconductors, power transfer efficiency is worst, and power dissipated is the most, when the device has to drop half the power supply voltage.

From this lesson, we can learn:

Semiconductor switch circuits should be either OFF or ON.

Semiconductor switch circuits should not spend any time in an intermediate condition

Semiconductor switch circuits will dissipate more heat if they spend any time in an intermediate condition.

Semiconductor switch circuits should be driven with sufficient drive level to ensure the switch will be able to reach a fully-ON condition, not depending on variations due to load resistance, individual MOSFET performance, and the like.

This is the reason we tied a pull up in the Basic Stamp example to a high enough voltage level (9-12V). Such voltage level at the gate would ensure that the MOSFET became fully open.

Furthermore, several key parameters change with temperature. Back to our datasheet, we see that all specifications given in tabular form are specified at “TJ = 25°C, unless otherwise noted”. J here is for “junction”, or device temperature.

From ID at Tc=100°C we see that the maximum current which the MOSFET can supply will decrease from 5.6A to 4A.

From IDSS (current from drain to source, with gate shorted to source) and Fig. 3, we see that leakage current will increase.

From Fig. 3 and 2 we see that a slightly higher VGS voltage (at the upper range) will be needed to have the device conduct the same amount of current, at a higher temperature. Although at the lower range of VGS voltage levels, more ID current will flow at the same voltage level.

From Fig. 4 we see that MOSFET ON resistance will almost double to 2Ω from an increase of junction temperature to 140°C.

Fig. 8 Defines SOA for the device (maximum product ID * VDS which can be applied to the device). For example, while our device has VDSmax=100V and IDmax=5.6A, this device cannot be operated at those two levels simultaneously, as it will exceed SOA. For a general guideline for a maximum product VDS * ID, use the PD specification (43W for this device).

And, Fig. 9 shows maximum drain current that the device will conduct, dependent on case temperature. During that region in which we have previously seen RON resistance double, IDmax will halve, to 2.5A. This is a good thing – all MOSFETS will increase their series resistance with increasing temperature, and allow less and less current to flow thru themselves. This will protect the device in those cases when it was not heatsinked adequately.

For the necessary information on how to choose a proper heatsink, visit Chapter 1 Special Insert – Thermal considerations.

Variability of parameters with temperature

I would like to reminder the reader again that all of the specifications listed in the datasheet are subject to variations due to temperature. An overheating MOSFET is very different from a room temperature list of device characteristics.

In particular, ID drops as power MOSFET heats up, keeping MOSFET safe, but supplying less power to the load. If you are operating anywhere near datasheets maximums at room temperature, you will exceed those values at higher temperatures (or not reach your circuit requirements).

VDD > VGS(max)

In our previous discussion, our supply voltages were around 10V. The benefit of this is the coincidence of such voltages not exceeding IRF510 VGS(max) if driving circuitry had to swing the gate all the way to VDD. But how can we drive a MOSFET properly at higher VDD voltages?

A separate driver supply rail is needed in this case. It can be, of course, regulated off the higher voltage rail, or taken from a separate power supply rail. You may ask about using the power rail of the digital portion of the circuit to drive the MOSFET driver chip. Unless large electrolytic capacitors are properly implemented for energy storage and noise filtering, that MOSFET driver may cause the digital portion of the circuit to become unstable or unreliable.

Fig 3.31

Be careful with high-voltage circuits, because VGS limit is relatively low! You can't always connect gate to VDD!

Sensing current

Fig. 4.32

When driving high power loads, it is a good idea to monitor undesirable conditions (short, overcurrent, load did not receive power, etc), because these conditions would be disastrous at high power.

A small resistance value sense resistor can be included between the source and COM, and voltage drop across that resistor measured (by an op amp, for example).

Driving inductive loads

Inductive loads are nasty loads because an inductor by definition resists any voltage level changes. That means it will try to oppose a voltage increase across it, as well as a decrease. What may seem like a small inductive load, of small current draw at DC (constant) voltage will require a lot more current if your intent is to increase that voltage from 0V to a high voltage quickly. Besides not being able to turn on an inductive load fast enough, the MOSFET will conduct a lot of current as well, heating up.

From the figure below, we can observe what the inductor does.

Fig 3.33

To turn an inductor on, current will start to flow from the top of the inductor to the bottom. If this is done quickly, an inductor will oppose that by “pushing” in the opposite direction, preventing us from increasing the current quickly.

A more serious matter happens if power supply to the inductor is disconnected. After we have the current flowing steady-state from top to bottom, but try to decrease it quickly, the inductor will oppose that change as well, and it will attempt to maintain that current flow. It will collapse its magnetic field, converting the stored magnetic field into electrical current, in the direction the current was flowing previously. What we get is a “battery”, creating a high voltage. Resulting voltage level, since that inductor is not loaded, can reach very high levels. A 12V relay briefly producing 100V is typical. More voltage will be produced by bigger inductors. For our circuits and loads, the resulting voltage spike depends on load inductance, power supply voltage, load current, and switch speed.

That voltage will be applied to the circuit according to the circuit below. Polarities specified are correct; by “opposing”, an inductor produces a voltage opposite to what you are trying to apply to it.

Since the transistor has already turned off, that voltage will not be dissipated. Instead, it will be applied to the circuit like so:

Fig 3.34

A transistor with a VDS=40V will be destroyed!

As for part numbers, that diode must: a) respond quickly b) withstand high voltage levels, and c) be able to dissipate all of that energy thru itself.

For our trivial loads and power supply voltages, a 1N4003 is sufficient. For driving larger loads or at higher power supply voltage, a Schottky diode (a fast diode) with appropriate breakdown voltages and surge current rating must be used.

I have seen circuits which do not use a flyback diode with the excuse that “a power MOSFET already has an internal diode”. While that is true for power MOSFETs (ratings of that diode are in the datasheet), that internal diode was not designed for flyback surge protection. Use of a fast diode next to the load (or PCB connection to the load) will ensure that flyback voltage will not even apply itself across the valuable and critical MOSFET.

From my experience, MOSFET failures are common due to driving an inductive or a shorted load.

Selecting a MOSFET with a proper minimum VDS

Issues such as inductive kickback, unregulated power supply output being higher than nominal by as much as 5V, etc illustrate why a safe margin must be used when selecting a MOSFET VDS for an application. It is a good idea, in a 36V circuit, to go with a 60V VDS rating, but only if the clamping network is guaranteed to clamp any voltage spikes well below VDS value.

Paralleling power MOSFETS

I have seen some circuit designers overdo one possible technique: connecting several MOSFETs in parallel. They are going for the following effects:

Smaller RON due to resistance paralleling

Higher current capability of the circuit

Ability to use a smaller heatsink (due to both a smaller effective RON and larger physical heat dissipating area of several MOSFETs)

I have seen a circuit where five MOSFETs were paralleled, no heatsink was used, and a fan was mounted to blow air at the TO-220 package all by itself. Commercial products will not overdo this technique due to the following problems:

High volume commercial designs save money by using the cheapest circuit components possible. Five MOSFETs is five times the cost of single MOSFET.

A mechanical fan is a single point of failure, and it will clog with dust eventually. What will happen to those MOSFETs if the fan fails? Will the circuit or the operator even know about the clogging?

Space is at a premium

While a heatsink is usually bulky and expensive, the metal electronic chassis can be utilized as a heatsink if necessary

Driver IC or circuit must work five times as much to drive five MOSFETs (more on this in the next section)

However, they fail to understand the way power MOSFETs are actually made. Power MOSFETs are basically many low power MOSFETs connected in parallel (drains to drains, sources to sources, gates to gates), in one package. The more MOSFETs in parallel internally, the less RON, and the bigger the IDmax. However, gate capacitance increases as well. Our RadioShack IRF510 had an IDmax of 5A, RDS(on) of 0.54Ω, and Ciss a measly 180pF. NXP Semiconductors PSMN2R2-40PS is a 40V, 0.0021Ω, 100A in the same TO-220 package. It only costs $2.77. Sounds interesting until you see a Ciss of 8423pF. Good luck trying to turn this beast on fast enough to take advantage of that RON! By the time it turns on if not driven by a specialized IC, you will waste power in the driver, and in I*R losses of the MOSFET coming on. And by the way, I don't think it is physically possible to put 100A in those TO-220 leads.

Instead of connecting four or five MOSFETs in parallel, try a more mild-mannered NXP Semiconductors PSMN8R0-40PS,127 with VDSmax=40V, IDmax=77A, Ciss=1262pF, RDS(on)=7.6mΩ, for $0.91. We will use this MOSFET in one of our practical circuits later.

Other than these remarks, MOSFETs can be connected in parallel (all source, drain, and gate terminals connected to respective terminals of the other devices) to either increase current-carrying capability or turn-on resistance. Just remember that simply choosing a different device or a bigger heatsink makes the technique pointless in most instances.

3.10 High frequency switching and dynamic effects

So far, we have seen our MOSFET switch high power loads without much effort from the controlling circuit (our 5k pot or the Basic Stamp). That is not the case if MOSFET must be switched on or off quickly.

At higher speeds, we will have an unwelcome effect appear: gate capacitance. The equivalent driving circuit then becomes:

Fig. 4.35 Equivalent circuit to calculate current needed to switch power MOSFET

We now see that the act of turning a MOSFET ON and OFF requires a charge and discharge of the gate capacitor CG. Because our driving circuitry has internal resistance RI, or is current limited (to perhaps 10mA for digital logic and microcontrollers), charging and discharging the capacitor quickly requires time and drive current.

An IRL510 datasheet lists gate capacitance as 250pF, and a “total gate charge” of 6.1nC, but to get the total capacitance, Ciss, Coss, and Crss must be added together. The IRL510 has a very poor RON of 0.54Ω. Devices which handle more current while exhibiting a very low RON have much larger gate capacitances, on the order of 1500 pF.

An approximate equation to find out how long the pause will be before the MOSFET turns on from a digital output signal is:

(using 5RC equation)

Qtotal = Icharge * Tcharge (using total charge equation)

With VG=5V, IGmax=5mA, Ctotal=345pF, Qt=6.1nC, turn on time delay would be something like 2μs. This is a rough figure. Remember that all datasheet specs are variable based on circuit parameters and conditions.

That happens when a MOSFET is turned ON. A more serious and damaging condition appears when a MOSFET is turned OFF. Should a feeble logic gate output decide to turn a MOSFET off, it will find itself in a world of hurt. Remember that capacitors pass non-DC current. And they do it from any direction. If a MOSFET is switched off, the drain will swing from a low value (open MOSFET), to VDD (closed). A capacitor is a two-way street! Effects from one side are passed on to the other thru the capacitor. A drain voltage swing will be transferred, and forced as current back into the driver output. This is called “gate capacitance dynamic current”.

Fig 3.36

Example: calculate the resulting current back into logic output if the MOSFET is turned OFF in the same amount of time as in the previous calculation, with a VDD=48V.

= 8mA

This current will be forced back into the logic output.

Gate resistors limit current to less than driver's current source capability, due to fast switching and fast drain voltage swings. A higher resistance value makes the driver work less, but it increases time delays, decreases speed and increases I*R thermal losses in the MOSFET. They are, therefore, a trade-off.

Explanations, illustrations, and formulae for turn-on and turn-off behavior can be found in Microchip Application Notes AN786 and AN898. I have included other relevant Application Notes and articles in an accompanying compressed file for this book.

Digital logic outputs do not like very much having currents being forced back into their outputs. Usually, they let out the blue smoke and give up. That is why a specialized MOSFET driver should be used. I have included a collection of datasheets. Read those datasheets to see what kind of conditions the devices are expected to withstand, to get an idea of what switching a power MOSFET entails.

3.11 N-channel MOSFET “upside down”

Readers will encounter situations where a statement is made such as "FETs are bidirectional. Source and Drain can be swapped. Signals of either polarity can be passed thru the MOSFET (power supply inverted)."

Or, they will see a circuit with a MOSFET having a load attached to source.

We will now examine both of these situations.

Firstly, other books and sources usually mix everything together, and use a dizzying number of terms interchangeably. They will mix JFETs, MOSFETs, N and P channel devices, body terminal (a fourth possible electrode that is not relevant to our discussion) as a separate terminal, and enhancement and depletion devices all in one chapter, reference them all by “FET”, jump from discussing one type to another randomly and abruptly, and then wonder why the reader is confused.

We are primarily dealing with power MOSFETs switching loads in this chapter, and power MOSFETs with body connected internally to source have a diode from source to drain. It cannot be flipped upside down.

The equivalent three terminal power MOSFET circuit, just like our datasheet reminds us, is Fig 3.7.

Fig 3.37

Flipping it upside down and connecting VDD to the top of the following device;

As you can guess, the internal diode will conduct uncontrollably and fully, shorting the load to VDD.

As for flipping the load from drain to source, that would create a different circuit type. The circuit on the right of Fig 3.38 becomes a “source follower”. We will discuss such a circuit in one of the next chapters on BJTs.

Fig 3.38

The two different circuits are referred to as high side and low side circuits. These terms indicate where the MOSFET is in relation to the load. So far, we have been looking at low side circuits where the MOSFET is below the load.

High side switching is a little more involved, because there are special requirements for gate voltage levels. As we have seen with high-side P-channel circuits, the gate voltage is referenced to source voltage level, not COM. The source in a high-side N-channel COM is connected to the load, not to COM. The problem appears when we consider proper gate voltages to turn a high-side N-channel MOSFET on and off. With VG=COM, the MOSFET is off. When it is off, however, connecting the gate to drain (or VDD) will not turn the device on, because since IL≈0, VS=VD=VDD. A level above VDD is needed, higher by the amount needed to turn the MOSFET fully on (10V perhaps). Therefore, another power supply is needed, or a trick we will see in Chapter 7.

3.12 Additional MOSFET notes and considerations

Testing a MOSFET. To test a MOSFET, do it only on an ESD table mat, with an ESD strap, and use a DMM with low-voltage resistance measurements, and diode check function. Deviating from the setup may destroy the device. With a DMM, resistances of all but one “lead to lead” combinations should be very high. There is no gate to drain or gate to source conduction, and the MOSFET is not ON. When making a source to drain measurement, a MOSFET will have a “built in” diode. This diode can be tested with the diode checker. There should be high resistance in a reverse diode measurement. If you see any other low resistance readings (<100Ω), or every lead seems to be shorted to every other lead, then the MOSFET is dead. Or, what you have is not an enhancement-mode MOSFET. If you have two pins with low resistance, but resistances from those two to the third are very high, then you may have a depletion-mode device. Read more about this below. In any case, attempting to read device label and looking it up on www.AllDatasheet.com is always helpful.

It is also possible to do a turn-on / turn-off test in most circumstances. If there is no gate to source (or COM) resistor, then the DMM can be used to charge and discharge the gate capacitor. The DMM used must have a diode check function. This function applies up to 5V do a DUT (device under test), at a low current, to check forward voltage drop of diodes and other similar devices.

Turn the unit off, and discharge high-power or high-voltage capacitors safely. Measure drain to source resistance. It should be a high value. Set the DMM into diode check function. Attach the red positive test lead to the gate, and red COM lead to source. Now switch to resistance check and measure the drain to source resistance. It will read a relatively low resistance, often near zero ohm. Switch back to diode check function, reverse lead polarity and touch the gate terminal. Measure resistance again. It will go back to a high value.

The test works for many devices because 5V is enough to turn on the FET, even if it is not a logic-level gate type, because RON is low for low drain currents even at a low VGS.

It is important to know about this test technique because it may crop up unexpected when DMM checking a MOSFET.

Further MOSFET testing can only be done in a separate test circuit, or right in its own original circuit.

Saturation region. Many other books and websites have nothing better to do than to call the active mode region a “saturation” region. Since this will only cause confusion when we discuss BJTs, this book will not do the same. I wanted to mention this so as to not have the reader confused when that term is encountered elsewhere. For MOSFETs, both “active” and “saturation” mode terms refer to exactly the same thing.

Choosing a MOSFET. I have a series of articles on choosing a MOSFET from an online seller on my website. Those articles clearly show how to narrow down the insanely high number of devices available to usable thru-hole devices with best parameters, at cheapest cost!

MOSFET protection. The reader will sometimes see voltage limiting devices between the gate and source, such as back-to-back Zeners to limit any transient voltage, or two diodes to the VDD and COM connections. These diodes are there for protection against either the driver over-driving the gate above VGS(max), or to limit spikes due to MOSFET turning off feeding back current into the driver thru the gate capacitor. If a specialized driver chip is used, these are not usually used to reduce circuit cost.

Body terminal. MOSFETs, especially the low-power kind can have a fourth electrode, called the body terminal. In most MOSFETs, especially high-power kinds, this is tied internally to the source, as you can see from the symbol. This is also that internal “diode” which we have been discussing, and saw on power MOSFET symbols. There are special circuit circumstances in which a device with four terminals is used, and that body terminal is connected to an appropriate voltage level.

MOSFET as a voltage controlled resistor is discussed by most books, but it is unlikely that the reader will have to build such circuits. In order to keep our discussion of MOSFETs lean, I have omitted discussions about such MOSFET behavior.

MOSFET as an amplifier, load line, Q point for MOSFETs. I do not like it very much when other textbooks put you thru the torture of confusing gibberish on the subject of using a MOSFET as a linear amplifier, and then tell you at the end “oh, you know, no one actually makes MOSFET amplifiers because they have high levels of distortion, and other limitations”. We will save this subject for devices which are actually used as amplifiers – JFETs (somewhat), and BJTs (best devices for amplifiers).

Same goes for depletion mode MOSFETs. Yet another opportunity to get confused by the different polarities and behavior. Only to either reach that statement at the end of the chapter, or to attempt to go online to buy one of these. Well, nearly no one makes or sells them, especially for high-power thru-hole device packages. Therefore, as far as I care, depletion mode MOSFETS DO NOT exist. If you want to know what a “depletion mode MOSFET” is – quite simply, it is a MOSFET which is ON (conducting) at VGS = 0V, and can be turned off by bringing the gate voltage up. Don't get terribly excited.

Improper MOSFET symbols and poor schematic layout and schematic capture skills in general are the reasons I don't sleep well at night. The problem is made worse by the great number of idiotic schematic capture software which only gets your money, but does not follow any standards and best practices. For the moment, I will only illustrate poor choices for MOSFET symbols.

Fig 3.39 There is something wrong with every symbol in this illustration

Just like with soldering, there is only one right way to do it, and a gazillion ways to do it WRONG.

For enhancement mode devices, the symbol must have a circle, and gaps to signify enhancement mode. It must have body terminal arrow. And it must include diode symbol for power MOSFETs as a reminder. Gate terminal must be positioned next to source.