Chapter 4 – JFETs (high input resistance amplifier)
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We have covered switch circuits with devices best suited for them – MOSFETs. We will now cover JFETs, which are best suited for high input resistance low-power amplifiers, which will be the sole focus of this chapter.
Fig 4.1
A JFET is a three-terminal device. Voltage at the third control terminal affects resistance between two terminals, called drain and source. This sounds like a MOSFET, and indeed JFETs are closely related to MOSFETs.
A functional representation of a JFET device is pictured on the left.
They are different from MOSFETs in the following:
They are available as low-power devices only. We are talking about plastic TO-92 cases or smaller, and PD=300mW, IDmax=30mA, VDSmax=50V.
They are depletion-mode devices. At no control voltage applied to the gate, they are fully ON (maximum current flows from drain to source). As the gate voltage is increased, RDS increases and JFET gradually closes to current.
Just like with power MOSFETs before, when we had to worry about a source-to-drain diode conducting, JFETs have a diode as well, this time connected to the gate, like our symbolic representation shows. This diode must not conduct in the forward direction with proper control voltages applied.
A note of total disclosure before we begin: Most of material in this section is relevant to MOSFETs in linear mode of operation, as well (as long as differences between these devices are kept in mind). I have chosen to treat MOSFETs as switches only, for clarity. They can serve other purposes as well, some if which will be covered here. This distinction is in place in order to prepare ourselves for the study of BJTs in the next chapter.
4.1 JFET gate diode
You must not make the gate diode conduct in the forward direction. Device connection in a circuit below will result in full and uncontrollable gate diode conduction, and device destruction.
Fig 4.2
Neither of the two circuits is a proper way to drive a JFET.
4.2 Class-A amplifiers, Quiescent point
Most phenomena in nature are of sinusoidal nature. The signal varies like so:
Fig 4.3
Where the vertical axis represents positive and negative amplitude, as shown, over a certain time period.
This represents phenomena all around us – light, sound, electromagnetic transmissions (radio), vibrations, etc. It would be beneficial for a circuit to accept such a signal, do a desired conversion (such as amplify the amplitude), and output a signal which is the same in general shape (i.e. it is still a sine wave). But how can we have a circuit which both accepts and produces negative voltage amplitude values?
Electrical engineers have come up with a simple dirty trick – class-A amplifiers.
Simple transistor circuits can accept and output only positive voltages. The trick is to shift that “0” point above circuit's 0V COM level. We can, for example, set a new reference point at ½ VDD, and reference the sine wave input from that point. Input signal can swing up and down in magnitude, adding and subtracting voltage to that new reference point.
Fig 4.4
Same trick is also done on the output of the circuit. Instead of outputting positive and negative magnitudes, the circuit is made to operate around a certain quiescent point, typically ½ VDD. If it goes above that point (highest it can go is VDD), we count that as positive magnitude, and if it goes lower than ½ VDD (lowest it can go is COM), we call that negative magnitudes.
The “dirty” part of the trick is the fact that a class-A amplifier is, without any input signal, centered at ½ VDD. It is drawing current to be kept at that point, and converts all of the energy it draws from the power supply in the quiescent point into heat. If the input goes high, so does the circuit, delivering maximum power to the load. If the input goes negative, the circuit turns itself off, delivering no power to the load. As you can remember from our discussion of switches, fully OFF and fully ON are desirable transistor operating points, because little heat is wasted in the device. A class-A amplifier draws power with a zero input, and its maximum energy efficiency is about 50%. The rest is wasted as heat in the heatsink. This simple but dirty solution is only appropriate at low power. Better methods exist for higher power, and we will explore those methods later.
I have still not explained how a negative output voltage is produced from a circuit. We use a capacitor for that. A capacitor does not pass DC (constant) current, but it passes changing or AC current thru itself. If a capacitor is attached to a point in the circuit which normally rests at ½ VDD or any other quiescent level, then there will be no voltage passing thru the capacitor. Should that voltage change, however, the capacitor will transfer that change thru itself.
Fig 4.5
Capacitor at the input serves another function, if our statement can be reworded. It is a blocking capacitor, since it blocks any voltages or currents at the input of the amplifier circuit (whatever they may be) from being passed back into input source. That amplifier input could be sitting at a hundred volts if it needed to be, while the input signal could swing it one volt more positive or one volt more negative, without knowing that it is applying itself to 100V, and without that 100V being connected back to the input.
4.3 JFET Class A low-power amplifier
For an N-channel FET, the basic control circuit is illustrated below. Build the circuit with a RadioShack MPF102. Resistor values are suggested ones, and can be changed a bit. Change the pot setting, and record your findings in your lab notebook. Plot ID (thru VOM) vs. VGS (DVM).
Fig 4.6
Fig 4.7
The linear-linear plot of ID vs. VGS is as pictured.
The plot tells us the same thing we have already seen experimentally from our circuit: JFET conducts with zero voltage at VG, and it turns off at VGS(OFF).
Time to look at a datasheet. And I must apologize at this point. The RadioShack device available, MPF102, has been named a “high frequency” transistor, and that is the way the datasheet for the device treats it. Do not attempt to obtain and view the datasheet for that device at this point in our discussion. Those infinite graphs can only be comprehended with an “expanded mind”. Neither do we have much choice from other sources. Digi-Key offers a grand total of three thru-hole N-channel JFETs. We will have to look at the datasheet for Fairchild J111, since it is the only one similar to MOSFET datasheets which the reader should be able to read by now.
Obtain the J111 datasheet online (from Digi-Key or AllDatasheet.com, or from the accompanying compressed file for this book), and follow along.
First, we have absolute maximum ratings and thermal characteristics. The reader should be familiar with what these are for, after having read the chapter on MOSFETs.
Then, we have “V(BR)GSS Gate-Source Breakdown Voltage”. Deciphering subscript notation, we see that this is “voltage, breakdown, from Gate to Source, with Gate shorted to Source”. This is stated at a negative 35V. We will revisit this negative value.
We then see “IGSS, Gate Reverse Current”. This is talking about that input diode at the gate. Since we are driving that diode “in reverse”, 1nA is how much current will pass into the device from the gate terminal. However, look at the test conditions: VDS = ID = 0V. Have you seen a circuit which can only operate on 0V? How useful is such a circuit? This is more marketing BS, picking most favorable test conditions for pretty specifications. That “input leakage” current will increase with increasing VDS and temperature.
We then have VGS(off) (Gate-Source Cutoff Voltage). This is input voltage level at which that JFET will close to current. We have already seen this voltage level from our experimental circuit, and the Fig 4.7 plot. Notice the huge spread in permissible values: -3...-10V. The manufacturer basically says “We don't know. Whatever”. Your purchased devices will have a value anywhere within that range. Do not think that this is acceptable. It is acceptable for hobby uses with circuits built by hand, and tested individually, but is not acceptable in a production environment, as every single circuit cannot be adjusted for JFET spread of characteristics. This characteristic may be called by several names, such as VT, VP "pinch-off” voltage, etc. We will use the VP designation.
There is also an “IDSS, Zero-Gate Voltage Drain Current”. This is the “fully open depletion-mode device at VGS = 0V” condition. Notice that the current is pretty small compared to MOSFET beasts we have been dealing with.
Since the reader will probably be using RadioShack's MPF102 device, we need to briefly look at its actual datasheet. We see that they also state their gate leakage current at unusable circuit conditions. Then we get to MPF102's IDSS. And what we see is “anywhere from 2mA to 20mA is OK”. This is simply incredible! The amount of current in the fully OPEN condition is given as a 10x spread. You, as a circuit designer, cannot count on using this JFET to build a circuit which must pass guaranteed 10mA of current. The device you will get may be unable to produce that much current.
This is a very big JFET limitation, and the reason they are not universally used. You have three choices if you build circuits with JFETs: a) adjust or test each unit by hand to adjust circuit operation or test that it will perform as needed, or b) sort JFETs which you purchase (by hand) for desirable specifications, before using them in a circuit, or c) design your circuit for low assumed levels ( ID 2...10mA). In the next chapter, we will get to devices which are much more predictable in their operation.
Do not attempt to view the rest of MPF102 datasheet, but return back to J111. We will now observe its ID vs. VDS parameters.
Fig 4.8
From our treatment of MOSFET characteristics, the reader should know to take this plot slowly, and to watch out for blood pressure or dizziness. All we need from this plot are the typical gate voltages to produce usable drain currents, and JFET device behavior. Notice that values in this plot are to not be taken seriously, but only the shapes of the plots, since the datasheet spread is:
“VGS(OFF) Gate-Source Cutoff Voltage VDS=5.0 V, ID=1.0 μA: –3.0 min…–10 max”
We also see that a single plot with a statement “typical VGS(OFF) = –2.0V” is given for all three devices covered by that datasheet. A pointless statement and a pointless plot to make, since that datasheet covers three devices with three different VGS(OFF) and IDSS.
What we get from all this discussion is the fact that calculating ID for a given VGS will not be reliable.
Notice also that the Fig 4.8 plot is mostly showing the “ohmic” region. In this chapter, we are interested in the horizontally flat curves area of the graph, the “active” region. These flat horizontal lines are at the far right of the plot, and VDS is not extended very much. The linear mode begins at VDS minimum for a linear amplifier of VGS – VP.
Enough of discussion, time to create some circuits. Looking at Fig 4.6 we see that the circuit given is not very practical because of the second negative power supply requirement. We want a circuit which can operate off a single power supply, but we cannot have the N-channel JFET gate diode conduct with positive control voltages. We use a trick again! That gate voltage is relative to source voltage. It must be lower than source voltage by a few volts. We can raise source voltage to above the COM voltage!
Fig 4.9
That 1M resistor just makes sure the gate sits at COM (so that it is not floating). It is also there to apply voltage to the gate by drawing a miniscule amount of current from the input, when the input is changing. At no input voltage, some quiescent current will be flowing thru the JFET. RS will create a voltage drop due to current passing thru it, raising VS above COM by the amount of the voltage drop thru itself. At this condition, the gate will be at a relatively negative voltage.
Looking at Fig 4.7 – with no Vin voltage applied, the transistor is closed; the gate will be at “a negative voltage”. Increasing voltage at the gate by the amount “Vgate-to-common”, up to the point “Vgate = Vsource” will turn the device ON fully.
We can now build a class-A, N-channel JFET amplifier! Putting everything we have discussed together, we get a circuit like so:
Fig 4.10
Input capacitor Ci is used to block DC but pass the signal frequencies. An electrolytic is commonly used, because it is cheaper and more compact at the capacitance values needed. Notice the polarity: relative to the circuit COM, voltage at the gate is a negative value. The input capacitor is therefore oriented with “+” side looking towards the voltage source (which is effectively a resistor to COM). For output capacitor, the “+” side is connected to circuit output, at which point there is a positive quiescent voltage.
IDSS, the maximum drain current
Before we can pick the quiescent drain current, we need to find out the maximum drain current which the JFET can conduct.
Since a JFET is a depletion mode device, the maximum drain current flows at VGS = 0V. However, the datasheet specifies this rating as VDSS = 2...20mA. This is an incredible spread!
Fig 4.11 Finding IDSS, the max current It is therefore beneficial to measure the device you have on hand. Measure its IDSS by setting VG=0V in our Fig 4.6 experimental circuit, for your particular JFET. However, an even simpler solution is to short the gate to source, and measure the resulting drain current. If you cannot build a circuit to measure it, assume a datasheet halfway value (to have statistical probability that your particular JFET will be able to produce this current).
Use ½ the IDSS value you have found experimentally, or what you have assumed from the datasheet, for the quiescent point. Two RadioShack devices which I had in stock had IDSS of 9mA and 5.3mA. I am going to use the 9mA device, making my IDQ of 4.5mA.
To experimentally find out ID vs VGS relationship, we are both going to plot our ID vs. VGS findings for our own devices, from Fig 4.6. I will show my findings; you can substitute your own. Task for the reader: find out the corresponding values for these important points:
VGS
ID
0
IDSS
0.3*VGS(OFF)
IDSS / 2
0.5*VGS(OFF)
IDSS / 4
VGS(OFF)
≈0
Fig 4.12
Note that we are working in the active mode, and the following discussion applies to active mode only. My plot for the 9mA MPF102 looks like the following:
VGS
ID
0
0V
IDSS
9mA
0.3*VGS(OFF)
-0.8V
IDSS / 2
4.5mA
0.5*VGS(OFF)
-1.4V
IDSS / 4
2.25mA
VGS(OFF)
-2.8V
≈0
0.1μA
Fig 4.13
This plot is given by the equation (valid only for JFET active region of operation):
,
if you know VGS. If you have ID (perhaps IDQ), and need to find VGS needed, the equation is:
Note that the plot looks just like a MOSFET plot, but is shifted into negative VGS values. This discussion also applies to depletion mode MOSFETs, as well as to some extent to enhancement mode MOSFETs in active region of operation.
Class-A amplifier component calculations
Let us figure out values for all components for our Fig 4.10 amplifier.
RG is only there to place the gate at Common potential. Its value is not critical. 100k-10M is a permissible spread. We will discuss its impact on the signal input shortly.
Rmic is a microphone datasheet requirement. We usually do what datasheets tell us to do. That resistor supplies power to an internal JFET pre-amplifier right inside the tiny microphone! The datasheet tells us to use a blocking capacitor, unless we want to feed a DC signal at VDD level into our input (due to Rmic).
The drain resistor should be chosen so that at a picked value of ID(quiescent), the drain sits at ½ VDD. We are just illustrating class-A operation in this circuit. We will discuss the range or permissible IDQ and VDSQ levels later.
I have hand-picked a 9mA IDSS device. To build a “most powerful JFET amplifier” I can use an IDQ of 4.5mA. The reader has to substitute their own findings. Therefore, for the source voltage offset (at Q point), we need VGS = –0.85V. RS==188Ω. The nearest 5% standard values are 180Ω and 200Ω.
For the 1/2VDD drain voltage quiescent level, RD==1k.
Choose Ci, Co. These are DC blocking capacitors, and we will choose them to not be an excessive impedance (resistance to AC frequency) for our application. We are building an audio range amplifier, so our 3dB roll-off frequency will be 10Hz. More on this in the next section.
CI (μF)==0.016 μF
However, we have not yet discussed other AC frequency operation factors (JFET gate input resistance, source output resistance, etc), which would decrease that RG value in the calculation. Increasing that value is a good idea, since that will only bring down the 3dB filter frequency. As a rule of thumb, use a ±10% standard value about 5x larger than what you obtain by these crude calculations. At small values, this can be a low-voltage ceramic capacitor, while at larger values an electrolytic is a cheaper option. If you need to use an electrolytic capacitor, its negative lead should be connected to the gate, and its voltage rating should be about 1.5 times VDD, as a rule of thumb.
Ci = 5*0.016 = 0.056μF (standard value)
For Co calculation, use RD. Co = 47μF (standard)
CS is a bypass capacitor. Use the exact RS value for its calculation. CS=100μF
Rmic is specified by the datasheet to be “up to 1k”. A bit ambiguous, so we will use 750Ω to be sure (or whatever resistor you have in the range of 600Ω-1k).
The circuit of Fig 4.10 with all the values calculated becomes:
Fig 4.14
Build the circuit. Before connecting the output, measure how much current the circuit draws from the power supply. Somewhere less than 10mA means that you did not create any shorts. Next, measure voltage at the drain. It should be about half the power supply voltage. Use a RadioShack “condenser microphone element” for input. Microphone pin which connects to the metal shielding is the COM connection. Plug in the output of this circuit into your computer's Mic input. You can reuse a wire from discarded headphones to interconnect between the circuit output and computer input. At the headphone wire, connect two colored wires together to the output capacitor, and two non-color shield wires to COM. Enable / turn on your computer's Mic input. Can you hear your circuit working if you speak loudly into the microphone?
Besides being a microphone pre-amp, this circuit can also work with sound instruments (guitar pre-amp, etc), as well as amplify “line in” sound levels. Test it with “line in”. Connect a “line” output as the circuit's input, and use the circuit's output as an input to another amplifier's “line in” jack. However, the large quiescent drain current is not at all necessary for such low-power applications. Redesign the circuit to work at IDQ of 1mA, and build your circuit nicely on a “prototype” PCB (the one with pre-drilled hole grid and a copper pad around each hole). Save it for those instances when you'll need a low-power amplifier, or as an accomplishment!
We now have to analyze this circuit in-depth.
4.4 Input and output resistance, impedance, and bandwidth
Let us examine the circuit again, with the input and output represented by resistances:
Fig 4.15
We will tackle input resistance first. Any signal source can be represented as a battery (which produces the signal), and a series resistance Ri. Many signal sources are low-power. If we connect that low-power source to a resistor of a value which is lower than Ri, a basic voltage divider will result. At DC current, we use the Ci blocking capacitor, however, it looks like a short for higher frequency AC signals. You can easily see that the gate in those instances is connected to the middle of a voltage divider. If the RG is of a low value, it will “load” the input source, decreasing its amplitude, and possibly distorting its output. Since we are using RG=1M, and JFET input resistance is high, we are not going to be loading sources with Ri up to 100k very much.
For reference, typical source resistances are:
Line out audio output: 10-100Ω
Microphone (condenser, with built-in JFET): 1k
Guitar pickup: 1M
At the output, we have the amplifier “output resistance”, 1k in our example. What this means is that we cannot “load” our circuit with a load of low resistance. If we connected headphones to the output, for example, with RL=32Ω, that would load the amplifier so much, that barely any voltage will be produced at the output. Since we connected our output to the computer's input (which should have input resistance of 100k-10M), we were not overloading the circuit.
You will encounter the term “impedance” often in electronics. This fancy term means “resistance considered at AC frequencies”. You are welcome to read about it elsewhere.
And finally, bandwidth. If you had studied circuit analysis before, you would realize that a capacitor output connected with a resistor to COM forms a high-pass filter. The capacitor freely passes higher frequencies, but starts to become a resistance at lower frequencies. At DC frequencies it stops to conduct any current whatsoever (open connection, or infinite resistance). We have to pick its value so that low enough frequencies are passed.
The equation to calculate 3dB roll-off point (read about this elsewhere) is:
Ccoupling, 3dB (μF)=
We are making circuits for audio frequencies (Hi-Fi is 20Hz-20kHz), so our 3dB point should be set to 10Hz.
4.5 Further circuit analysis
Before we head off changing the circuit, let us study further what we already have. We still haven't found out what the gain (amplitude of output divided by amplitude of input) of our circuit is.
Gain, or amplification, is what we were looking for from a microphone pre-amplifier. Gain is needed because a microphone cannot drive a speaker. The differences between different sources of voltages are:
Radio antenna: 1μV max
Microphone output: 1mV max
Line level: 1V max
Headphones: 3V at 300mW, 32Ω
Small speaker: 4V at 2W, 8Ω
To convert microphone input to headphone output, the voltage has to be amplified at least 3000 times. Also, the circuit must have a low output resistance, and a relatively high current/power output.
JFET device gain changes with ID. We can find its value at a particular point with an equation:
This is also the datasheet gfs value. If it is given as "mmhos", which means "milli" mhos. Mho is a unit, which is "ohm" spelled backwards. Look it up! The overall voltage gain of the circuit can then be found from:
For our circuit, overall voltage gain is:
Firstly, why the minus? Because a positive input voltage opens the JFET to more current flow. Consequently, it becomes a lower resistance. Since our JFET class-A amplifier is a voltage divider with the drain resistor RD, a lower JFET “resistor” value decreases VD. The output swings in the opposite direction. The minus just means that our JFET amplifier will invert the signal.
And secondly – why such a low value? We built a whole JFET circuit, and calculated a three inch equation just to find out that for an input of 1mV, our circuit would produce a measly 5mV!
This is why we had to plug our circuit into the computer mic input. It would not amplify the signal anywhere near a thousand times in order for us to be able to plug it into “line in”. What if you needed more gain than 4.5x? What if you needed to build, for example, a microphone to “line in” amplifier? You have three choices:
Do not use JFETs. In the next chapter, we will cover devices which have much higher amplification.
Connect two or more amplification stages in series. When you do so, the gains are multiplied together. For example, if the second stage had an amplification of 5.5, then the overall amplification is 5.5 x 4.5 = 25.
Operate at a different quiescent current. We will cover this in the next section. This will only increase the gain slightly, however.
In actuality, what we have built was not an amplifier, but a pre-amplifier. It has low gain, so a pre-amplifier is not for “volume amplification”. But it has high input resistance and lower output resistance. It will, therefore, not load the input source very much, and will drive the input of another amplifier with ease (next amplifier will not “load” the JFET pre-amp, presenting signal shape and amplitude).
Besides the already stated reasons, we can introduce two applications for this circuit:
1) A pre-amplifier for a microphone, the output of which would have to run a hundred feet to reach the mixer board. The circuit would prevent signal drop and noise pickup, due to the cable length.
2) Guitar pre-amplifier. Guitar pickup has a 1M output resistance. If we use the “microphone” input of the mixer board, that input was designed with a 1k microphone output resistance. It will “load” guitar pickup output, decreasing its amplitude. Our circuit would “isolate” or “convert” that high signal source resistance to a resistance a thousand times smaller. Gate resistor RG would have to be increase in value, of course, so that it does not load guitar pickup resistance.
Circuit limitations
Our circuit was built for small input voltage swings. High voltage swings will cause the following undesired effects:
1. Gain of the circuit, and a few other values will change with drain current swings. This will introduce non-linearity (distortion).
2. Clipping will occur if the output cannot generate a swing which is gain times the input swing. If our circuit had a gain of 10, and an input voltage of 1Vp-p (peak to peak) was applied at the input, then since the output can only swing ±0.5*VDD, it would not be able to output a sine wave with 10Vp-p magnitude. The output it will create will look like:
Fig 4.17 Clipped sine wave
3. Same “clipping” effect is present on the input as well. Our gate is sitting at a quiescent value of -0.85V. An input swing of 1V would place positive voltage at the gate. Because of the gate diode, positive control voltages 0...0.6V should not be applied to the N-channel JFET gate, and voltages more than 0.6V must not be applied.
Since our quiescent point was 0.3*VGS(OFF), bigger negative swings in the input are allowed than positive ones are. A positive swing of 0.85V is allowed, while a negative swing of 1.95V is OK, if the circuit can output an undistorted signal (perhaps with a larger supply voltage). That quiescent point can be moved to 0.5*VGS(OFF), but the quiescent drain current, and maximum output current will decrease as well.
4. The circuit must be kept in active region. VDS cannot swing all the way to COM. Remember from our MOSFET discussion that our circuit must be kept out of the left side of the Fig 4.8 plot.
Let us examine these circuit limitations in more depth.
4.6 Range of permissible IDQ and VDSQ levels
That quiescent point, which we talked about, can be set anywhere on the Transfer Function plot. However, the choice will impact circuit operating limitations. For a class-A circuit, the range of permissible swings can be visualized like this:
Fig 4.18
Where Vin is just a 90º rotated plot (electrical engineers love to cram too much information into plots). What we are looking for is the range of allowable "wiggle" at the input and output, which will keep us within the graph. As you can see, selecting IDQ at 1/2 IDSS allows for the maximum drain current swing in either direction.
If a maximum Vin swing was required instead, VSQ should have been set to 1/2 VGS(off).
From the gain equation , we can see that gain can be increased by increasing RD. As we can see from the plot, that would constrain us to smaller allowable ID swings. Picture moving the dot down along the plot. Vin will shift to the right along with the change, and ID intercept will move down as well. (IDQ – 0) allowable swing will then be less than what is current shown on the plot.
> More output current, lower output resistance
> Largest input and output swing
> Higher gain, higher RD, lower output current
Fig 4.19
Higher drain resistance, as we have already seen, will increase circuit output resistance. Any connected load with a resistance less than 10 times RD value will load the circuit, and decrease actual gain. Therefore, we can only improve the gain of our circuit somewhat (because of the typically low JFET gain).
We are additionally limited in our circuit by the active region constraint. Revisit Fig 4.8 again. In order for our circuit output to only depend on the VG input voltage, it must stay in the active mode, where the lines are flat in relationship with VDS (a value on which an amplifier's output should not depend!).
The requirement to stay within active mode of operation is: VDS>(VGS-VTH)
In order to stay within active mode, voltage drop across the device, VDS must satisfy:
Fig 4.20
For our class-A circuit with self-bias the equation can be rewritten as:
Where VG is the input signal, and VD is voltage at the drain, as it drops from its quiescent value towards COM. After creating a circuit, verify that it its output will be linear, by satisfying:
Output Swing (Input swing times circuit gain) < Permissible Swing (VDD – VDQ and VDQ – COM)
Drain voltage (VDQ – output swing) > (Input voltage + VGS(off))
4.7 P-channel JFET
There is a type of a JFET which allows us to build a circuit more like MOSFET circuits we have seen. The type also uses positive gate control voltages. It's a P-channel JFET.
P-channel JFET ID vs. VG plot shows positive VGS control voltages:
Fig 4.21
We see that no “negative” control polarities are needed, and the basic circuit becomes:
Fig 4.22
This circuit satisfies gate diode drive requirements. Voltage VG ≥ 0V.
If this circuit looks so simple to understand, and looks like circuits we have dealt with in the chapter on MOSFETs, then why didn't we start with P-channel JFETs? Because they have the same limitations as P-channel MOSFETs when compared to N-channel MOSFETs: Slower speed, higher RON, lower ID. Additionally, while I have said that fewer of P-channel MOSFETs are made, it is even worse with JFETs. Few N-channel JFETs are made (MOSFETs have become more popular), and P-channel JFETs are nearly non-existent, especially for non-SMD parts. Of the parts which are thru-hole (non-SMD), in-stock, with low minimum quantities, and not with EOL (end of life) notices, Digi-Key lists none, Allied has one type (NTE326), and Mouser has two types (J175_D26Z and 2N5460).
4.8 Further notes and circuits
1. Remember that voltage gain for a JFET amplifier is relatively low, and decreases further with input and output resistances attached. To increase gain, RD or supply voltage can be increased, but circuit output resistance will be higher. If the next stage or input has a relatively low input resistance, then increasing RD further will not be a good idea.
2. JFET parameter spread is very large. Remember the specified IDSS of 2...20mA of our part, while two devices I had on hand showed 9mA and 4.5mA. Additionally, VGS(off) is an important parameter, and it is specified to be “-8V max”. Trying to design a circuit with a meaningful drain current while being able to accommodate devices with unknown VGS(off) spec is not possible. Once those two specs are actually measured, everything else can be calculated (device gain gfs, circuit gain, Q point range, etc). However, testing each device before use and modifying a circuit accordingly is not realistic for production environment.
3. In general, source and drain terminals of a JFET can be switched places, unless the datasheet says otherwise. Drain can act as a source, and vice versa.
4. Homework: design, build, and test a JFET amplifier with the following specs: RG=10M, VDD=12V, RD=10k. Everything else will depend on your JFET parameters. What is your circuit gain? This circuit will make a fine guitar pickup pre-amp with an output resistance of 10k. It will work fine unless what it is being plugged into has an input resistance less than 100k. A modern mixer board should have high resistances, but a guitar amp on bipolar transistors or a tube amp will not!
5. You will see circuits elsewhere which show two gate resistors. One goes to COM (like we did), but the second one goes from gate to VDD. This is an alternative method to bias a JFET. You are free to read about it elsewhere.
6. Datasheet gfs (forward transconductance) is specified at IDSS. This is a gain specification, and its units are Siemens (S) or mho. It is usually given in milli Siemens (mS), or milli mho (mmho). This gain decreases with decreasing drain current, so you cannot use the datasheet spec blindly.
7. Input leakage, given in the datasheet, is the current flowing into the gate diode (in the opposite direction to forward conduction). This current sets the low limit for the gate resistor. Gate resistor should be chosen so that it does not drop input voltage source level by more than 10% ().
However, the marketing department always picks the most favorable conditions, this time being at VDS = ID = 0 (!) and 25ºC. This current increases exponentially with increasing temperature, and doubles every 10ºC.
Testing a JFET with a DMM
A JFET will have a low resistance between the Source and Drain terminals, in both directions. There will be a “diode” from the gate to the other two terminals, which can be tested with the DMM diode check function. The only way to tell a drain from the source is to identify the JFET from its markings, and look up its datasheet.
MOSFET as an amplifier
In special cases, a MOSFET can function like an amplifier. It will have the benefits of high power, lower RON, very high gate resistance, and no gate diode effect. However, I do not care about MOSFETs as an amplifier because of low gain, huge parameter spread, and high distortions. In the next chapter we will study another transistor which is perfectly suited for high-gain or high-power amplifier functions, among others.
